Metal-oxide-semiconductor (MOS) devices are basic building elements in integrated circuits. Many methods have been explored to improve the performance, such as reducing threshold voltages, of MOS devices.
FIGS. 1 through 5 illustrate cross-sectional views of intermediate stages in the manufacturing of a conventional complementary MOS (CMOS) structure. FIG. 1 illustrates silicon substrate 2, including NMOS region 4 and PMOS region 6. High-k gate dielectric layer 8 is blanket formed on silicon substrate 2, followed by the formation of n-metal layer 10. Hard mask 12 is then formed and patterned to mask the NMOS region 4. In FIG. 2, dielectric layer 8 and n-metal layer 10 are removed from PMOS region 6. Silicon substrate 2 is also recessed in PMOS region 6, forming recess 7. Silicon germanium layer 14 is then epitaxially grown in recess 7, as shown in FIG. 3. Next, as illustrated in FIG. 4, high-k gate dielectric layer 16, p-metal layer 18, and hard mask 19 are blanket formed. In FIG. 5, high-k gate dielectric layer 16, p-metal layer 18, and hard mask 19 are removed from NMOS region 4.
The stacked layers shown in FIG. 5 may be used to form gate stacks for an NMOS device (not shown) in NMOS region 4 and a PMOS device (not shown) in PMOS region 6. The channel region of the resulting PMOS device is thus formed of silicon germanium layer 14. Advantageously, the threshold voltage of the PMOS device is reduced. In addition, compared with a PMOS device having a silicon channel, the hole mobility of the PMOS device with the silicon germanium channel is greater. The drive current of the PMOS device formed in PMOS region 6 is thus improved.
The CMOS devices formed using the above-discussed method, however, suffer from drawbacks. The channel region of the NMOS device formed in NMOS region 4 has no strain coming from the underlying substrate, and thus the drive current of the NMOS device is less than optimal. Further, the germanium in silicon germanium layer 14 may diffuse into high-k dielectric layer 16, causing a leakage current in the resulting PMOS device. New formation methods are thus needed to improve the drive currents of NMOS devices and to reduce the leakage currents of PMOS devices.